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Re: exception priority for BCM1250

To: Lijun Chen <>
Subject: Re: exception priority for BCM1250
From: Ralf Baechle <>
Date: Wed, 31 Mar 2004 01:43:42 +0200
In-reply-to: <>
Original-recipient: rfc822;
References: <>
User-agent: Mutt/1.4.1i
On Tue, Mar 30, 2004 at 05:47:41PM -0500, Lijun Chen wrote:

> Does anybody know which mips family SB1 core on bcm1250 falls into?
> It is a MIPS64 processor, does it belong to 5K family or 20Kc?

They're all MIPS64.

> What about the exception priorities, such as cache error exception, bus 
> error exception, and so on? Are they maskable or non-maskable? It is not
> clear from BCM1250 and sb1 core manuals.

This is explained in the MIPS64 spec.


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