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Re: gcc support of mips32 release 2

To: Ralf Baechle <>
Subject: Re: gcc support of mips32 release 2
From: Goswin von Brederlow <>
Date: 24 Mar 2004 13:38:27 +0100
Cc: Geert Uytterhoeven <>, "Maciej W. Rozycki" <>, Dominic Sweetman <>, Eric Christopher <>, Long Li <>, Linux/MIPS Development <>, David Ung <>, Nigel Stephens <>
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <> <> <> <> <>
User-agent: Gnus/5.0808 (Gnus v5.8.8) XEmacs/21.4 (Reasonable Discussion)
Ralf Baechle <> writes:

> On Fri, Mar 19, 2004 at 11:42:11AM +0100, Geert Uytterhoeven wrote:
> > > Take a look at the 68020 to see where instruction set madness can lead:
> > >
> > >   movel   ([42, a0, d0.2*2],123), ([43, a0, d0.2*2], 22)
> > >   bfextu  ([42, a0, d0.2*2],123){8:8}, d2
> > 
> > These instructions didn't complete in 1 cycle, while the new RISCies do.
> That's the point, they went overboard with their C^2ISC philosophy.  These
> instructions were more or less unusable by compilers of the time and the
> given the rarity were not the most performant instructions of the
> architecture either, so made sense only relativly rarely.  So in the end
> the didn't get it right in the beginning which lead to the removal of the
> instruction in 060, if I recall right.
>   Ralf

Thats a

 move.l 31530(A0, D0*2), 5675(A0, D0*2)  (that would give a bus error)

before assembly right?

That instruction is great to access array or aligned structure members
with an offset and compilers should be able to generate it for it. But
its only realy usefull if your short on registers, which gcc does not
optimize for.

Don't think they got removed. Could it be you are thinking about
mulu.l d0,d0:d1   (32*32=64 bit mul) and the like?


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