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Re: gcc support of mips32 release 2

To: "Maciej W. Rozycki" <>
Subject: Re: gcc support of mips32 release 2
From: Dominic Sweetman <>
Date: Mon, 22 Mar 2004 09:42:32 +0000
Cc: Dominic Sweetman <>, Eric Christopher <>, Long Li <>,, David Ung <>, Nigel Stephens <>
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <> <> <> <>

> > Insert/extract make a reasonable case for themselves, but actually
> > arrived in MIPS32 release 2 as part of a bunch of other bit-shuffle
> > instructions (also includes rotates and various byte-swaps) which -
> > together - help quite a bit to manipulate sub-word data in registers.
>  I see.  Actually all of them are a bit redundant, often replaceable with
> short sequences of other instructions, but I guess code compacting may
> matter more for the embedded environment than for general-purpose
> computing.

When we relied on things like Specmarks for benchmarks, those are
mostly general purpose C programs.  They tend to be intricate
programs, not dominated by repetitive handling of large-scale data
(the floating point benchmarks *are* data-intensive, which is why 
architectural strangeness is much more successful on those).

Moreover, Specmarks have a strong tendency to use 'int' data types;
sub-word data handling is essentially irrelevant to performance on
them.  RISCs are good at the fiddly stuff (at least, well-designed
RISCs are) and happy with the int data types: so the Specmarks are
relatively good and we're happy.

But an important sub-class of embedded workloads are data intensive,
where the data represents some sort of stream.  Basic data items are
often 8- or 16-bits in size.  Existing RISC instruction sets end up
bloating the inner loops of these programs, and it's marginal
performance gains rather than code size which motivates us to make
this work better.

>  And while we are at instruction usefulness -- why are there the "di" and
> "ei" instructions, but there is no a complement instruction, say "si" (for
> "set interrupts"), that would copy bit #0 from a GPR to
> compactly and atomically?

The 'di' is there to be atomic.  Such sequences are rare and code
compactness is not an issue.  As you probably heard before, the use of
a potentially-interruptible RMW sequence on the status register to
disable interrupts is potentially troublesome (most common OS' manage
themselves so it isn't an issue, but still...)

The 'ei' comes for free with it.

In encoding terms, di/ei can be seen to be individual members of a
generic instruction whose action is something like "atomically
set/clear bit in a CP0 register".  But CP0 registers are low-level
things, whose bits have real hardware functions; so implementing the
bit-set/bit-clear is not the same in all cases.  So we've defined
this instruction minimally, only or critical bits.


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