Hi Dominic Sweetman,
> > > Basically, the PC points to the next
> > > to
> > > be executed. But, in R4k, there are 8
> > > getting executed in parallel. Where does the PC
> > > to? My understanding is that PC points to the
> > > instruction that will be entered into the
> > > Please correct me if i am wrong..
> Ralf Baechle (email@example.com) writes:
> > The fact that instructions are issued in a
> pipeline is not visible in
> > the EPC value.
> Which is true, but perhaps a bit cryptic given the
> A MIPS CPU does not have a register called "PC". In
In the r4k user manual, it is mentioned that there is
a special register PC in the core CPU (other than the
HI & LO special registers). Could you please let me
know the purpose of this register?
> the MIPS
> architecture, "PC" is just slang meaning "the
> address of this
> instruction" - and only makes any sense if you're
> prepared to say
> WHICH instruction you mean.
> There IS a register called "EPC" (for "exception
> PC"). When you
> take any kind of exception, it's the address of the
> first instruction
> which didn't get run because the CPU took the
> exception instead. So
> EPC tells you where to jump back to after the
> exception handler runs.
> Did any of that make any sense?
> Dominic Sweetman
> MIPS Technologies.
The expert at anything was once a beginner
O / Karthikeyan.N \
O | Chennai, India. |
`\|||/' \ Mobile: +919884104346 /
(o o) \ /
_ ooO (_) Ooo____________________________________
Yahoo! Messenger - Communicate instantly..."Ping"
your friends today! Download Messenger Now