The cache size is modified by setting the IC/DC
bits in the 'config' register. Seems they are set only
by the hardware during the processor reset. And also,
those bits are mentioned as read only bits..
Could you please let me know how can we instruct
the hardware to do so. Can we do this via s/w?.
The expert at anything was once a beginner
O / Karthikeyan.N \
O | Chennai, India. |
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