[Top] [All Lists]

Re: Regarding branch delay instructions in R4000

To: "Kevin D. Kissell" <>
Subject: Re: Regarding branch delay instructions in R4000
From: "Maciej W. Rozycki" <>
Date: Mon, 22 Dec 2003 13:47:52 +0100 (CET)
Cc: karthikeyan natarajan <>, Michael Uhler <>,
In-reply-to: <01e801c3c6e2$4aa51ff0$10eca8c0@grendel>
Organization: Technical University of Gdansk
Original-recipient: rfc822;
References: <> <01e801c3c6e2$4aa51ff0$10eca8c0@grendel>
On Sat, 20 Dec 2003, Kevin D. Kissell wrote:

> Yes, MIPS stood for Microprocessor without Interlocked Pipeline Stages
> when it was first used as a name for a graduate student project at Stanford
> University in publications from 1982.  But that in itself was a play on words,
> as the most common metric of computer perfomance at the time was 
> "Millions of Instructions Per Second", or MIPS.  The Stanford architcture 
> was revamped and commercialized as the "MIPS I" architecture, implemented 
> in the R2000 and R3000 CPUs, which likewise had no interlocks on cache load 
> delays. As silicon geometries became finer and gates got cheaper, the 
> relative cost
> of providing the interlocks decreased, while the need to run the same MIPS 
> binaries on multiple, very different implementations of the architecture 
> increased.
> So from the R4000 onwards, MIPS CPUs have had interlocks.  But by that time
> the name "MIPS" was a well-known trademark, and it made no sense to change it.

 Well, as I like to nitpick, actually the original MIPS I R2000 and R3000
processors did have a single interlock already -- the one used for reading
the HI and LO registers. ;-)

+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+        e-mail:, PGP key available        +

<Prev in Thread] Current Thread [Next in Thread>