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Re: MIPS Interrupts.

To: "Kapoor, Pankaj" <>
Subject: Re: MIPS Interrupts.
From: Ralf Baechle <>
Date: Wed, 26 Nov 2003 00:09:46 +0100
In-reply-to: <>
Original-recipient: rfc822;
References: <>
Resent-date: Wed, 26 Nov 2003 00:27:43 +0100
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User-agent: Mutt/1.4.1i
On Tue, Nov 25, 2003 at 04:52:20PM -0500, Kapoor, Pankaj wrote:

> Now there are 2 cases that can happen 
> 1. Since we have not exited the ISR and the exception level has still not 
>    been restored there can be no more interrupts that are generated in the 
>    system. In such a case does that mean that the all bottom half handlers 
>    pending execution will run with interrupts disabled. 
>    NOTE: This does not seem likely because the local_irq_enable routine
>    calls _sti which clears the exception level in the status register and
>    also sets the IE bit. 
> 2. If we have large number of tasklets or if the bottom half handlers take
>    time to execute, then we could get another timer interrupt or other
>    device interrupts causing context saves which would cause the stack to
>    grow and CRASH the system. 

Interrupts are disabled while the respective interrupt handler is running.


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