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is cp0 interrupt infrastructure sufficient..?

Subject: is cp0 interrupt infrastructure sufficient..?
From: "ashish anand" <>
Date: 17 Nov 2003 11:40:11 -0000
Original-recipient: rfc822;
Reply-to: "ashish anand" <>
I have a generic question regarding interrupt controler functionality 
integrated in CP0 on mips architecture.
I don't see any interface to configure the edge/level triggering settings.

though in our BSP we take care of handling spurious interrupts , but is
this designed to be like that..?

I mean to ask , suppose I want to add a edge triggering peripheral 
, to the extent of my understanding this will certainly generate the
spurious interrupts when coupled with a level triggering configuration 
in CP0 (by default..?).

if i am handling through CP0_CAUSE or any other register inspection
that can work but I am loosing so many valid interupts which would have been 
really valid with edge trigger pin of interrupt controller  .
further this type of handling is valid for actual spurious interrupts 
not for those who are certain to be fired because of edge/level mismatching.

Best Regards,
Ashish Anand

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