> I met a problem when debuging a bootloader in IT8172G+RM5231A platform, it's
> like this:
> the bootloader had 2 parts, the first part executes in ROM
> (0xbfc00000-0xbfc0xxxx) and
> it move another part from ROM into SDRAM, then jump to the SDRAM entry point
> to continue.
> In the ROM resident code, if I initialized&flushed the cache, it can jump to
> SDRAM entry
> continue normally. However,if I comment out those cache related code and make
> cache disabled,
> it seems can not jump to SDRAM entry.
> Who can tell me why I must initialize&flush when cache disabled ?
Precisely what do you mean by "cache disabled",
and what is the address of the SDRAM entry?