On Tue, Dec 17, 2002 at 02:35:22PM +0000, Dominic Sweetman wrote:
> > The i8259A doesn't work this way. With your proposed code the IRR
> > is never cleared (which is a problem for edge-triggered interrupts
> > -- such an interrupt gets signalled again once it's unmasked, until
> > deasserted by a device). The i8259A only clears a bit in the IRR
> > when it receives an ACK (it then copies the bit to the corresponding
> > bit of the ISR) or when an interrupt goes away (a device deasserts
> > it).
> Just a few comments on the hardware:
> As I recall, you can clear a stored edge-triggered interrupt using a
> "specific EOI". In the 8080 microprocessor for which the 8259 was
> designed, this command was magically communicated to the 8259 when the
> CPU ran its "return from interrupt" instruction. I think even in the
> 8086 this had to be replaced with an explicit I/O cycle.
> People not using x86 CPUs should consider putting the i8259 into
> "special mask mode". Then it behaves simply and predictably,
> providing an interrupt on any active unmasked input. You lose the
> i8259 interrupt priority stuff, but this is only one of the
This sounds a lot like the doc I read when I did the programming. Does
anybody know *the doc* I am talking about? I can't seem to find it anymore.
Meanwhile I find myself cannot answer Maciej's question as to when IRR
bit is cleared under edge triggering case. Perhaps the hardware does it
automatically when IRQ is generated?
I will probe further and reply to you later.