On Fri, Nov 29, 2002 at 02:03:00PM +0100, Maciej W. Rozycki wrote:
> BTW, how do you know that ll/sc happens to work for uncached operation on
> some processors? Maybe it simply fails, but the result is subtle enough
> not to be observed easily. A failure may be masked by other factors, e.g.
> for the UP operation, there is normally no way for two parallel requests
> for a spinlock to happen and an exception resets the LLbit regardless of
> the caching attribute of the area involved.
That's a consequence of the simplemost way to implement ll/sc in hardware.
ll puts the physicall address of the the memory reference into c0_lladdr
and sets the ll-bit. eret clears the ll-bit and finally sc fails if the
ll-bit is cleared. That's the simplest implementation for a non-coherent
uniprocessor, there is not much more needed that a flip-flop and due to
every designers desire for simplicity a different implementation seem
unlikely. Btw, c0_lladdr is just a useless gadget here.
It's different for coherent processors, those actually need to snoop on
the bus interface. On those the simplest implementation is ll generates
a cache line in exclusive state; sc then fails if either the ll-bit has
been cleared; the snooping logic clears the ll-bit if the cache-line's
state changes or an eret is executed. So the mechanism fails without