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Re: Promblem with PREF (prefetching) in memcpy

To: Carsten Langgaard <>
Subject: Re: Promblem with PREF (prefetching) in memcpy
From: Dominic Sweetman <>
Date: Fri, 4 Oct 2002 14:29:24 +0100 (BST)
Cc: Dominic Sweetman <>, Ralf Baechle <>,
In-reply-to: <>
Original-recipient: rfc822;
References: <> <> <>
Carsten Langgaard ( writes:

> >  "PREF does not cause addressing-related exceptions. If it does happen
> >   to raise an exception condition, the exception condition is
> >   ignored. If an addressing-related exception condition is raised and
> >   ignored, no data movement occurs."
> Is a bus error exception an address related exception ?


I agree some MIPS documentation has been ambiguous on the
subject, probably because from the chip designer's point of view the
address is generated early and internally, and the data turns up
later.  It's ambiguous whether the BadVaddr register will be correctly
set on a bus error (it is on most Big MIPS CPUs, I believe).

But that's beside the point.  PREF should plainly never cause an
exception because of a bus error.

> I'm afraid some implementation think it's not.

That would be a bug.

So let's suppose you've got that bug.  And you've got a program
running in cacheable memory, and PREF wanders off the edge of the

If you were running mapped, you surely wouldn't have a spurious
cacheable mapping to single-cycle memory...

In kseg0, you might step into a different physical address region.
It's good practice to reserve a 'guard' area of address space between
general memory and I/O registers, of course.  If the hardware doesn't
do it, maybe the software could, by simply refusing to allocate the
highest addressable 4Kbytes of memory for general purposes.

Some systems idly decode a cache refill in a non-memory region as one
or a sequence of reads, causing a bus error.

I count that as one CPU bug and two system misfeatures.  The solution,
I guess, is a "bogus bus error" handler.

> What about an UART RX register, we might loose a character ?

Yes, without a guard region and with cache refills cheerfully decoded
to bogus single-cycle reads, you can get bogus reads.  With a
careless-enough memory map, you might read something with a side

> You can also configure you system, so you get a external interrupt
> from you system controller in case of a bus error, there is no way
> the CPU can relate this interrupt to the prefetching.

Yes, that's true; interrupts on bus errors are vaguely useful for
post-mortem diagnosis, but useless for recovery.

Dominic Sweetman, 
MIPS Technologies (UK) - formerly Algorithmics
The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
phone: +44 1223 706200 / fax: +44 1223 706250 / direct: +44 1223 706205

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