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Re: Cycles for certain instructions

To: Gareth <>
Subject: Re: Cycles for certain instructions
From: Dominic Sweetman <>
Date: Fri, 20 Sep 2002 12:15:03 +0100 (BST)
In-reply-to: <>
Original-recipient: rfc822;
References: <>

> I am doing an investigation with a mips malta board that has a 4kc
> processor on it. I am trying to find out how many cycles certain
> instructions take to execute.
> The program I am running loops a small piece of code many
> times. After a few loops of the code the caches will have all the
> instructions in them and so accesses to memory will be few and far
> between.

Some 4Kx CPUs have write-through caches.  If yours is one of them,
write traffic will continue to flow to memory.  There's a FIFO on the
CPU to hold write address/data, but unless your writes are sparse the
FIFO will rapidly fill, and the program will run only as fast as the
memory can process the writes.

4Kx CPUs with writeback caches can still be configured with the cache
disabled or (in some cases) in write-through.

> So how many cycles do instructions such as load word and store word
> take?

One.  But the operation is pipelined: if you try to use the data you
loaded in the very next instruction, the CPU will wait one extra clock.

Strange things may happen if you put loads shortly after a store to
the same location.

> Obviosly if the data is not in the cache the time take will depend
> on the speed of the external memory.


> If the data is in the cache is the time taken fairly predictable for
> a given core?

Very predictable!

Dominic Sweetman, 
MIPS Technologies (UK) - formerly Algorithmics
The Fruit Farm, Ely Road, Chittering, CAMBS CB5 9PH, ENGLAND
phone: +44 1223 706200 / fax: +44 1223 706250 / direct: +44 1223 706205

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