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Re: [patch] MIPS64 R4k TLB refill CP0 hazards

To: Ralf Baechle <>
Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards
From: "Maciej W. Rozycki" <>
Date: Wed, 31 Jul 2002 13:34:17 +0200 (MET DST)
Cc: Carsten Langgaard <>,,
In-reply-to: <>
Organization: Technical University of Gdansk
On Wed, 31 Jul 2002, Ralf Baechle wrote:

> Nope, on R4000 four cycles are needed between the tlbwr and a eret
> instruction; on the R4600 just two.

 Ugh, I missed this entirely, thanks for pointing it out.  The doc implies
three cycles for the R4000 actually, though. 

+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+        e-mail:, PGP key available        +

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