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Quick Q about caches

Subject: Quick Q about caches
From: Jason Gunthorpe <>
Date: Sat, 12 Jan 2002 01:05:30 -0700 (MST)
Hi All,

I've been working on some cache code for a new processor and I just
quickly wanted to ensure I'm reading the existing stuff right, I hope that
someone who knows a bit more about this codes history could just confirm
some of my guesses :>

So here is what I'm thinking: (read virtually indexed == cache aliasing

The stuff in c-mips32 is for a processor with virtually indexed primary
and secondary caches, seperate i/d caches and no io-coherancy

The stuff in c-rm7k describes a processor with physically indexed
caches, but seperate non-snooping i and d caches. The IO coherancy stuff
does too much flushing, notably DMA should never be done to regions that
are executing, and the flush_scache also does the flush_dcache as in
c-mips32 (presumably this is what the XXX comment is talking about)

The SB1 reference tells me that it has a virtually indexed icache that
also tags ASID's, the CONFIG_VTAG_ICACHE option invokes the special code
to manage this ASID caching. The rest of the caches are physically indexed
and IO coherant (woop!). The comment for sb1_flush_page_to_ram does 
not jive with the stuff in Documentation/cachetlb.txt - I think the
latter is right and the function should be a nop on a physically tagged

The one thing I don't quite get yet is why flush_dcache_page is a NOP for
everyone? That must mean the dcache is always physically indexed if
Documentation/cachetlb.txt is correct.. 

Anyhow, the chip I've got is largely sane, the only annoyance is that 
the SR7100 has physically tagged but virtually indexed i/d-caches that
can alias if the page size is less than 8K, the rest seems 


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