On Mon, 7 Jan 2002, Phil Thompson wrote:
> I am working with some hardware that has a "feature" that I'd like some
> advice on how to handle. The PCI bridge has a read-ahead buffer between
> the PCI bus and system memory - used by PCI bus masters. The buffer can
> only be invalidated from software.
Geeze best put 'pci bridge' in quotes too, that's totally not allowed by
the PCI bridge spec. Delayed transactions and any data that the bridge
may prefetch have very specific lifetimes. Hardware that does what you
describe is very much non conforming..
Are you sure of what you are seeing?
> Is this "feature" common? Is there existing code I can look at?
No - it's a bug not a feature :>
The best you can do is have any write to a PCI io/memory space from the
CPU clear the prefetch buffer, and hope you don't hit any of the other
anomolies that can show up.