> But, how does MIPS 5kc work with 32bit Linux kernel?
If the KX, UX, and PX bits of the CP0 Status register
are all zero, a MIPS5Kc is essentaillly functioning as
a 32-bit CPU. The registers are still 64 bits, and
arithmetic operations will cause all 64 bits of the
destination to be written, but this is outside of the
"event horizon" of the program so long as 64-bit
data and addressing is not enabled. The 64-bit
5Kc can, and does, boot the same Linux kernel as
the 32-bit 4Kc. MIPS64 is a strict superset of MIPS32.
> Do you means there is no difference between 32 bit
> mode and 64 bit mode for MIPS 5kc in kernel mode?
There is no such thing as "32-bit mode" and "64-bit
mode", not really. There are 64-bit data-type instructions
(e.g. "LD", "DADD") and, logically independently, there
is 64-bit addressing for loads and stores - which includes
LW and LB as well as LD. 64-bit data is always enabled
in kernel mode on a MIPS64 part. For 64-bit data in User
mode, and for 64-bit addressing in *either* mode, there are