> -----Original Message-----
> From: Zhang Fuxin [mailto:email@example.com]
> Sent: 19 September 2001 09:38
> To: firstname.lastname@example.org
> Subject: Re: Re: 8259 spurious interrupt (IRQ1,IRQ7,IRQ12..)
> hi,Jun Sun，
> 在 2001-09-18 10:09:00 you wrote：
> >Zhang Fuxin wrote:
> >> hi,all
> >> I have finally been able to get a copy of sgi cvs
> code:).Now I have
> >> changed my p6032 code to use new[time,pci,irq] code and it seems a
> >> lot cleaner.But still problems.
> >Cool. Very glad to hear that.
> Thank you for encourage:). I am new to mips and kernel
> programming,the code
> may still look very dirty for your eyes.But i will try my best.
> >> I keep seeing spurious interrupt when starting xwindows.And
> >> sometimes without x. If the machine is doing heavy io(e.g.,unzip &
> >> untar mozilla source) when I startx,it will probably enter an
> >> endless loop of spurious interrupt or lead to unaligned instruction
> >> access shortly after(with epc=0x1,ra=0x1) and die.
> >> I have seen spurious IRQ1,IRQ7 and IRQ12,and the endless
> loop case
> >> is IRQ12--ps2 mouse interrupt.
> >> Can somebody give me a clue? What I know is that 8259
> may generate
> >> spurious IRQ7 & IRQ15. But how can the others happen,buggy hw?And
> >> what may cause a kernel unaligned instruction access?
> >Are you using arch/mips/i8259.c file?
> >One possibility is your irq dispatching code. If it loops
> to deliver all
> >pending interrupts, what you described may happen (assuming
> there is a real
> >hardware connecting to those irq sources).
> I have checked the p6032 manual.It says it has an intel
> FW82371AB("PIIX 4")
> south bridge chip,a National Semiconductor PC97307-ICE/VUL multi I/O
> controller which includes dual serial ports and rtc,PC
> mouse/keyb etc,connect
> to the PIIX 4.
Make sure you read the section in the P6032 manual "Tips on programming
south bridge interrupt controller(s)" - page 31. I don't see how the 8259
code that's part of the MIPS tree can ever be used without changes.