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To: Jun Sun <>
From: "Maciej W. Rozycki" <>
Date: Mon, 25 Jun 2001 15:22:11 +0200 (MET DST)
Cc: "Kevin D. Kissell" <>,
In-reply-to: <>
Organization: Technical University of Gdansk
On Sat, 23 Jun 2001, Jun Sun wrote:

> I think you just proposed a fix: check current config register when we turn
> off cache.  Thanks. :-)

 Note that many MIPS CPUs do not have the config register that could be
used to turn the cache off.  That's not a problem for the userland as it's
controlled on a page-by-page basis, but the kernel runs unmapped (except
from modules) and user vs kernel memory coherency problems arise.  I have
a patch that makes the kernel run in the KSEG1 space (which is uncached by
default even on processors that have the config register).  It needs a
minor clean-up for exception handlers, though, as they start in KSEG0 with
no possibility to override.  So they should jump to KSEG1 ASAP --
hopefully two icache lines are OK; if cache in non-functional then we are
screwed as using bootstrap exception vectors is not an option, usually.
Cacheability of KSEG0 may be further disabled if possible. 

 I'll send the patch soon, when I clean it up.


+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+        e-mail:, PGP key available        +

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