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Re: Multiple processor support?

To: <>, "Matthew Dharm" <>
Subject: Re: Multiple processor support?
From: "Kevin D. Kissell" <>
Date: Sat, 24 Mar 2001 01:40:47 +0100
Cc: <>
References: <> <>
> > Well, I'd like to know about both, frankly.  Tho I'm more interested
> > in whichever is designed to run on RM7000 series processors.

None are "designed" as such for the RM7000.  I don't have a
full RM7000 manual in the shop, but the short-form advance
manual that I do have, while it goes into a fair amount of
detail about the cache operations and external interface
protocols, makes no mention of any support for hardware
coherence of the sort provided by the R10000/R12000
(and the R4000/R4400 for that matter).  If there is no support
for cached/coherent memory attributes and cache interventions
from the system side, an SMP kernel design for an MP SGI box
might not be useful for an MP RM7K configuration.  It is possible,
but tricky, and at times unavoidably inefficient to build a
software-coherent SMP system.  I have not heard of anyone
doing so with MIPS/Linux.

> To the best of my knowledge, the mips64 tree only works in SMP on the
> which is r10K based.  There would be a bit of work to get an RM7K  based
> multiprocessor system to run. A fair amount of the "generic" code in
> that tree is also pretty ip-27 specific, and so would need to be cleaned
> I'm working on mips32 SMP support at the moment; there are no existing
ports of
> this tree to an SMP platform.  The mips64 stuff is certainly much, much
> mature.  I don't know of any reasons not to use the mips64 side for an

Well, one reason might be memory footprint...


            Kevin K.

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