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Re: R5000 support (specifically two-way set-associative cache...)

To: Dominic Sweetman <>
Subject: Re: R5000 support (specifically two-way set-associative cache...)
From: Jun Sun <>
Date: Fri, 30 Jun 2000 18:22:58 -0700
References: <> <> <> <> <>
> Fundamentally:
> o "index" operations just go first through one set, then the other.
>   So long as initialisation routines are applied to each possible
>   index in turn, both sets get initialised.
> o "hit" operations "just work".
> So long as initialisation is done carefully (basic rule: perform one
> stage to the whole cache before going on to the next), run-time cache
> maintenance can and should be done with "hit" instructions, and you
> don't need to worry whether the CPU is direct mapped, 2- or 4-way set
> associative.
> (it's all explained in my book, "See MIPS Run", of course...)
> Even with the Vr5432 you only have to know the difference when first
> setting up the CPU.

Not exactly - the current Linux/MIPS implementation uese index
operations to flush cache.
As a result flush_all_cache() does not really flush all cache.

> Dominic Sweetman
> Algorithmics Ltd


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