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Re: R5000 support (specifically two-way set-associative cache...)

To: Jun Sun <>
Subject: Re: R5000 support (specifically two-way set-associative cache...)
From: Dominic Sweetman <>
Date: Tue, 20 Jun 2000 21:59:32 +0100 (BST)
Cc: Dominic Sweetman <>,,,
In-reply-to: <>
References: <> <> <> <>
Jun Sun ( writes:

> I meant to talk about Vr5000 but I was looking at the Vr5432 manual!
> 1. both CPUs have two-way set-associative caches
> 2. Vr5432 uses vAddr:0 to select the way

The Vr5432 is indeed different, compelling you to be aware of the
number of sets.

> 3. I am not 100% sure about Vr5000.

It uses a high-order bit, just like R4600.

> > Can someone familiar with R4600 tell us more about how R4600 cache
> > is setup to hide two-wayness?  Thanks.


o "index" operations just go first through one set, then the other.
  So long as initialisation routines are applied to each possible
  index in turn, both sets get initialised.

o "hit" operations "just work".

So long as initialisation is done carefully (basic rule: perform one
stage to the whole cache before going on to the next), run-time cache
maintenance can and should be done with "hit" instructions, and you
don't need to worry whether the CPU is direct mapped, 2- or 4-way set

(it's all explained in my book, "See MIPS Run", of course...)

Even with the Vr5432 you only have to know the difference when first
setting up the CPU.

Dominic Sweetman
Algorithmics Ltd

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