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Re: Icache coherency problems for R3400, DS5000/240

To: "Maciej W. Rozycki" <>
Subject: Re: Icache coherency problems for R3400, DS5000/240
From: Ralf Baechle <>
Date: Tue, 20 Jun 2000 00:04:55 +0200
Cc: Ralf Baechle <>, Harald Koerfgen <>,,
In-reply-to: <>; from on Mon, Jun 19, 2000 at 11:31:27AM +0200
References: <>
On Mon, Jun 19, 2000 at 11:31:27AM +0200, Maciej W. Rozycki wrote:

>  Working on gdb I discovered a weird behaviour of my DS5000/240 -- under
> unspecified circumstances there were spurious breakpoint traps happening
> and some single-step breakpoints appeared persistent.  The following patch
> fixes these problems, making gdb fully reliable.
>  Besides obvious bugfixes, it introduces two significant changes.  First,
> flush_icache_page() now performs what the name suggests, i.e. flushes the
> instruction cache.  Without this change ptrace(PTRACE_POKE*, ...) calls
> are unreliable.  Second, it changes the assumption of the icache line size
> to a single word -- apparently, at least R3400 of DS5000/240 has an icache
> with such a layout (DEC docs confirm it, indeed).  Without this change,
> there are problems with breakpoints placed at addresses equal 4 modulo 8. 
>  I vote for an immediate inclusion of these fixes.

Looks good unless one of the R3000 gurus objects, so I'll add this right
after my ac21 commit finishes.


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