At 10:56 AM 6/2/99 -0700, William J. Earl wrote:
>Robert Keller writes:
> > At 12:46 AM 5/28/99 +0200, Ralf Baechle wrote:
> > >The R5000 is supported and known to work. You happen to have a
> > >second level cache on that board?
> > how convinced are people that the VR5000 is supported? I'm running
> > the latest code off the linux.sgi.com cvs server and I'm getting *very*
> > weird page faulting problems when doing the kernel/user space
> > hazard shuffle. Its really hard to describe the problems as they are
> > not deterministic: sometimes the right thing happens, other times
> > I get restricted instruction exceptions... Both of these can happen on
> > the very same kernel binary...
> What sort of system are you using, and what is the hardware
>configuration (including caches)?
Its an NEC 5074 development board with an VR5000 --
32K I and 32K D Primary cache
no secondary cache.
which vec0 code should I be using?
NEC seems to have a bunch of errata and hazards in this part when
dealing with TLBWR and friends... Is any of the existing code supposed
to respect these?
Also, arch/mips/Makefile makes the compiler use -r8000 -mips2, is