On Wed, Sep 02, 1998 at 05:58:15PM +0200, Ulf Carlsson wrote:
> On Wed, 2 Sep 1998 firstname.lastname@example.org wrote:
> > As I recently told you on IRC - the patch as you've posted it is not
> > correct. It will misstreat VCEI exceptions.
> My idea is based on that we write the wrong cache line back, and that's
> why we receive the invalid instruction errors.
> Maybe this is foolish, but anyway: If we have data from main memory cached
> in the secondary cache and then overwrite that data line in main memory
> with an instruction line and cache the instruction. We receive a VCEI when
> we try to access the cached line, and our handler writes the data back
> instead of the intstruction and causes the invalid instructions. Well,
> this is the only idea I have at the moment.
Note that we don't have to care about if the line contains data or
instructions. All we know is that the l2 line corrosponding to the
instruction which threw the vcei exception is in some state other than
invalid. We cannot accidently writeback an instruction line to memory
because the Hit_Writeback_Inv_SD cacheop we're using will only write
dirty lines back.