[Top] [All Lists]

Re: R5000 caches

Subject: Re: R5000 caches
From: "David S. Miller" <>
Date: Thu, 11 Sep 1997 00:09:23 -0400
In-reply-to: <> (message from Ralf Baechle on Thu, 11 Sep 1997 05:51:07 +0200 (MET DST))
   From: Ralf Baechle <>
   Date: Thu, 11 Sep 1997 05:51:07 +0200 (MET DST)

   Can anybody give me a pointer to where the R5000 caches, especially
   the cache instruction, are documented?  My two IDT R5000 manuals
   don't contain the least bit of information regarding the cache
   instruction.  I'm primarily interested in how the indexed
   operations select the cache set of the primary caches to operate
   on.  On the R4600 which has 16kb per cache bit 13 selects the set.
   So I assume it's bit 14 on the R5000 with it's 32kb per cache?  The
   code from David handles the R5000 like a R4000 CPU but this doesn't
   look very credible to me as this is a QED CPU and the other members
   of the R5k family like the Nevada (which run Linux now also!) have
   two way primary caches.

In SGI boxes, if my memory serves, the R5k's were the chips which
needed the special:


sequence, both to enable/disable the cache and to perform flush
operations.  Although this could have been for the R4600.  I do
remember that IRIX had special code to work the R5k caches, but this
might have been for the L2 cache operations only, not L1.

All of this was very SGI specific and was mostly for the L2 cache
operations.  I think the R5k had a special "flush command" which would
just pull a pin going to the cache and invalidate all the lines in one
cycle (earle told me this, he may be able to elaborate).

The R5k, by design at least in the SGI boxes, lacks a L2 cache, it was
added externally on the SGI motherboard's, and thus all the funcy
methods to access/enable/disable/flush it...  Again, I could be
confusing r4600 and r5k here, so who knows.

David "Sparc" Miller

<Prev in Thread] Current Thread [Next in Thread>