To: | Carsten Langgaard <carstenl@mips.com> |
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Subject: | Re: [update] [patch] linux: Cache coherency fixes |
From: | Ralf Baechle <ralf@oss.sgi.com> |
Date: | Fri, 2 Aug 2002 12:38:05 +0200 |
Cc: | "Maciej W. Rozycki" <macro@ds2.pg.gda.pl>, linux-mips@fnet.fr, linux-mips@oss.sgi.com |
In-reply-to: | <3D4A4191.DF5EFFC4@mips.com>; from carstenl@mips.com on Fri, Aug 02, 2002 at 10:23:53AM +0200 |
References: | <20020801152500.A31808@dea.linux-mips.net> <Pine.GSO.3.96.1020801173504.8256H-100000@delta.ds2.pg.gda.pl> <20020801184929.B22824@dea.linux-mips.net> <3D4A4191.DF5EFFC4@mips.com> |
User-agent: | Mutt/1.2.5.1i |
On Fri, Aug 02, 2002 at 10:23:53AM +0200, Carsten Langgaard wrote: > The Malta board is a system that both run coherent and non-coherent, so I > would prefer, that we either make the coherency a configuration option or > make it possible to determine at run time. Definately the latter then. The price to pay is small and I don't think forcing the use to change the kernel when just changing CPU modules is acceptable. Ralf |
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