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Re: [patch] MIPS64 R4k TLB refill CP0 hazards

To: "Ralf Baechle" <>
Subject: Re: [patch] MIPS64 R4k TLB refill CP0 hazards
From: "Kevin D. Kissell" <>
Date: Wed, 31 Jul 2002 09:28:09 +0200
Cc: "Carsten Langgaard" <>, "Maciej W. Rozycki" <>, <>, <>
References: <> <> <> <> <00f801c237c6$29cabd00$10eca8c0@grendel> <20020731040529.A5451@dea.linux-mips.
From: "Ralf Baechle" <>:
> Basically we have two groups of interrupt handlers.  Some contain
> workarounds for hardware bugs; the rest are very similar except having
> to handle different hazards.  I was already thinking about building the
> actuall exception handlers from a piece of code that inserts the right
> number of (ss)nops etc. as required into the right place, thereby
> producing an optimal handler for every CPU.

I really don't think that's a good idea.  That implies that we
could no longer simply inspect the exception handlers in
the source code or disassembled kernel binary file to 
analyse them for correctness, and I think it would lead
to unnecessary and hard-to-find bugs.  My personal
recommendation would be to keep the model we have
today, wherein handlers are selected at boot time from
some set of candidates built into the kernel binary, with
the slight modification that the templates be loaded into 
the init segment, so that the memory consumed can be
reclaimed at run time.  That would eliminate the only
argument I can see against having a larger set of 
statically-built optimized handlers.  The current
selection process is ad-hoc based on CPU ID.
We could easily formalize that a bit, and even
provide a boot command line option to override
the automatic selection with something "safer".


            Kevin K.

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