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Re: load_unaligned() and "uld" instruction

To: "Jun Sun" <>
Subject: Re: load_unaligned() and "uld" instruction
From: "Kevin D. Kissell" <>
Date: Fri, 6 Oct 2000 00:10:18 +0200
Cc: "Ralf Baechle" <>, <>, <>, "Dominic Sweetman" <>
References: <> <> <> <000d01c02782$32d31560$0deca8c0@Ulysses> <> <> <> <00d101c02f04$3a6d7340$0deca8c0@Ulysses> <>
Jun Sun wrote:
> "Kevin D. Kissell" wrote:
> >
> > > > > Ralf, before the perfect solution is found, the following patch
> > > > > the gcc complain go away.  It just use ".set mips3" pragma.
> >
> > Which, as Ralf correctly observes, will generate code that will
> > crash on 32-bit CPUs,
> Why will it crash 32-bit CPUs?  On my R5432 CPU, the lwl/lwr sequence
> executes just fine.
> Or do you mean it will crash SOME 32-bit CPUs?  Do those 32-bit CPUs
> support lwl or lwr?  If they don't, they should generate a reserved
> instruction exception.  If they do, I don't see any problem.

Please re-read my previous message.  I wasn't talking about the
MIPS I lwl/lwr sequence for loading an unaligned 32-bit word, I was
talking about the MIPS III ldl/ldr sequence for loading an unaligned
64-bit doubleword.

            Kevin K.

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