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Re: Icache coherency problems for R3400, DS5000/240

To: Ralf Baechle <>
Subject: Re: Icache coherency problems for R3400, DS5000/240
From: "Maciej W. Rozycki" <>
Date: Wed, 21 Jun 2000 12:35:01 +0200 (MET DST)
Cc: "Gleb O. Raiko" <>,
In-reply-to: <>
Organization: Technical University of Gdansk
Reply-to: "Maciej W. Rozycki" <>
On Tue, 20 Jun 2000, Ralf Baechle wrote:

> > Why did you change name of bits in CP0 regs ?
> The R3000 was using the R4000 naming of the bits.

 Hmm, that's weird.  It means my "IDT MIPS Microprocessor Family Software
Reference Manual" is bogus.  But their definitions seem to have a
background, given the bits have different meaning for R3K and R4K+.

 They state (these are not citations but shortly explain what they mean): 

- CP0.SR.bit16 is IsC (Isolate Cache) for R3K, where it disables line

- CP0.SR.bit16 is DE (Disable ECC?) for R4K+, where it disables cache ECC

- CP0.SR.bit17 is SwC (Swap Caches) for R3K, where it swaps icache's and
dcache's roles,

- CP0.SR.bit17 is CE (Check ECC?) for R4K+, where it enables checking
of cache ECC bits via the CP0.ECC register.

 This sounds reasonable -- i.e., why bits with a different semantics would
have the same names?  Isn't that correct?

+  Maciej W. Rozycki, Technical University of Gdansk, Poland   +
+        e-mail:, PGP key available        +

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