Maciej W. Rozycki (email@example.com) writes:
> > Yes, the original R3000 chip could be wired to produce the appearance
> > of multi-word lines in its I-cache, and some derivative CPUs were built
> > that way. Four was popular - I don't think anyone did 8.
> DEC docs claim the cache subsystem of KN03 is configured with single-word
> lines for the icache, but upon an icache fill the MB ASIC fills four
Ah, I'm suffering from muddy memory syndrome.
You're quite correct: on the R3000 cache every word had a tag, but an
I-cache refill could be setup to fill several of them at once -
implicitly storing the same tag in each position. I believe it was in
theory possible to gently remove the two lowest tag addresses, use a
smaller tag memory, and have a genuine four-data per tag I-cache. It
would have behaved very strangely while swapped for
> OK, by "flush" I always meant "invalidate" (see also ia32's invd and
> wbinvd instructions -- the first one causes an external flush
I should have realised that Linux ab-usages usually refer to x86
technology. Thanks for that.