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Re: Icache coherency problems for R3400, DS5000/240

To: "Maciej W. Rozycki" <>
Subject: Re: Icache coherency problems for R3400, DS5000/240
From: "Gleb O. Raiko" <>
Date: Mon, 19 Jun 2000 14:24:53 +0400
Organization: NIISI RAN
References: <>
"Maciej W. Rozycki" wrote:
>  Besides obvious bugfixes, it introduces two significant changes.  First,
> flush_icache_page() now performs what the name suggests, i.e. flushes the
> instruction cache.  Without this change ptrace(PTRACE_POKE*, ...) calls
> are unreliable.  Second, it changes the assumption of the icache line size
> to a single word -- apparently, at least R3400 of DS5000/240 has an icache
> with such a layout (DEC docs confirm it, indeed).  Without this change,
> there are problems with breakpoints placed at addresses equal 4 modulo 8.
>  I vote for an immediate inclusion of these fixes.

Why did you change name of bits in CP0 regs ? It seems it's possible to
get the patch functionality w/o such a change. Morover, the changes in
the icache line size assumption
are already there, in 2.3. What is a version of linux you patch is
against ?


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