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Re: VC exceptions

To: Ralf Baechle <>
Subject: Re: VC exceptions
From: Dominic Sweetman <>
Date: Sun, 30 Apr 2000 11:56:03 +0100 (BST)
Cc:, Florian Lohoff <>,,,
In-reply-to: <>
References: <> <> <>
> On Sat, Apr 29, 2000 at 06:33:54PM -0400, wrote:
> > What is a r7000?  I've heard of the r8000, is that the same?

Ralf's right about the R8000, which was something like a vector
floating point unit (lots of parallelism, special FIFO caches) bolted
to an R4000+ integer unit.

The "R7000" is really called RM7000, designed and sold by QED
(MIPS-the-company doesn't let its licensees use Rx000 names).  QED is
a small company one of whose founders designed the R4000.

QED's first contract (around 1993) was to design the R4600 for IDT to
manufacture.  QED went on to design the R5000 for MIPS (same integer
core, faster FPU, bigger caches).  QED's designs tend to be simple and
clean, which keeps power consumption low and clock rates up.

The RM7000 is QED's big development.  The core is a bit more
sophisticated than an R5000 (it can issue two instructions in the same
clock cycle under more circumstances), but the main innovation is a
256Kbyte on-chip secondary cache.

R10000 was designed by MIPS for Silicon Graphics.  A contemporary of
"Pentium Pro" it uses the same out-of-order mechanisms, and was
probably the first OOO machine to run properly, making it briefly the
fastest microprocessor on the market.  

So the R10000 was desperately complicated, and the RM7000 is simple
but has onchip secondary cache.  At the same clock rate, the R10000 is
going to be much faster (and use much more power, and cost much more
to build into a system).  I doubt if even the just-announced 400Mhz
RM7000 is really faster overall than a 180MHz R10000 - but Ralf might
have access to some measurements.

Dominic Sweetman

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