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Re: Indy SC bug

To:, Ralf Baechle <>
Subject: Re: Indy SC bug
From: Ulf Carlsson <>
Date: Tue, 11 May 1999 08:04:56 +0200
In-reply-to: <>; from Ralf Baechle on Tue, May 11, 1999 at 01:00:18AM +0200
Mail-followup-to:, Ralf Baechle <>
References: <> <>
On Tue, May 11, 1999 at 01:00:18AM +0200, Ralf Baechle wrote:
> On Mon, May 10, 1999 at 08:56:40PM +0200, Ulf Carlsson wrote:
> > I've found a silly bug in the R4600SC caching routines. It wiped the
> > whole cache at wrap arounds even if you just tried to write back two
> > cache lines (for example the last cache line and the first cache
> > line).
> > 
> > I can't understand how this bug has lasted so long in the
> > kernel. Well, now that I've sorted it out, your R4600SC machine be A
> > LOT faster.
> The asm constraints are wrong as well, will commit a path.

I think that round up macro is quite useless. For example if you want to write
back line 0, wouldn't indy_sc_wipe(0, 0) do it just fine? Now, even if you just
want to write back the sillies little bit of data, two cache lines are written
back. This is also the cause of the wrap arounds (which actually shouldn't
happen the comment tells me).

- Ulf

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