> > The code which loads the wired entries into the tlb is borken. Somewhen
> > during the startup the c0_wired register is set again to zero.
> does this mean, that there are no wired entries installed for Magnum boards
> (the code looks like this) ? How will such a kernel work ?
Well, the code *should* install them. For the SGI port David shreddered the
code that loads the wired TLB entries and I did´t fix that so far.
> sorry, I don't quite understand that. Do you want to get rid of the wired
> entries, because 48 TLBs aren't enough for normal usage ? Do you want to
> use page faults to map hardware registers ?
Using TLB misses would be the right thing to use. But in case of the
Jazz machines and the current kernel this won´t work. The current
page table format has the limit that it can only map to physical addresses
in the 0 <= x < 512mb range. These addresses are also accessible through
KSEG0 and KSEG1, so we never need to use the TLB.
For everything outside the lowest 512mb address space we have the options
to use wired TLB entries or 64 bit pointers. If we extend the size of
a page table entry to 64 bit we will also have the preferable option
of using the normal TLB faults at hand.