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Re: working 2.1.36 on magnum/m700 ?

Subject: Re: working 2.1.36 on magnum/m700 ?
From: Dom Sweetman <>
Date: Tue, 3 Jun 1997 08:52:00 +0100 (BST)
In-reply-to: <>
References: <> <>
You probably mostly know this, but...

Ralf wrote:

> > Maybe a got time to get rid of those entries?  48 entries is just
> > not enough to wire many of them.

And Thomas said:

> sorry, I don't quite understand that. Do you want to get rid of the
> wired entries, because 48 TLBs aren't enough for normal usage ? 

> Do you want to use page faults to map hardware registers ?

Most MIPS systems reach hardware registers through the fixed kseg1
uncached window (onto physical memory from 0 to 512Mbytes).  The
kernel works mostly in kseg0, the fixed cached window onto the same
address range.  

If your system is bizarre enough to put hardware registers outside
this easily-accessible physical address range, you would indeed need
either special TLB entries (or real 64-bit pointers on an R4x00).  In
this case not even Ralf would disagree with wiring those entries; but
a better solution would be to fire the hardware designer and
incinerate the hardware.

A few permanent "wired" TLB entries are typically used for some
critical kernel resources which must for some reason be mapped, but
where you can't tolerate a TLB-miss exception.  

MIPS note: a TLB miss is not a page fault.  TLB misses just reload the
TLB from some memory-resident data structure.  On a CISC CPU this
would be handled 'invisibly' by microcode, and it really doesn't make
much difference to have it done by an exception.

A page fault is where the data you want is not valid in memory, and
the OS needs to be invoked to find what data is appropriate, find it
(perhaps on disk) and map it.

Dominic Sweetman

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