[Top] [All Lists]

Re: Delay Slot

To: linux-mips
Subject: Re: Delay Slot
From: "David S. Miller" <>
Date: Mon, 14 Apr 1997 23:43:09 -0400
In-reply-to: <> (message from Elias Kesh on Mon, 14 Apr 97 19:52:41 -0700)
   Date: Mon, 14 Apr 97 19:52:41 -0700
   From: Elias Kesh <>

   Can someone explain to me what a delay slot is ? Twice now I have had to 
   change code from this

 [ ... ]

   in order to get the right arguments at the other end. I am using gcc 
   2.7.2-2 and the processor is a 4300 from NEC.

Here is another case where they massively messed up the programmer
level interface to coding on the MIPS.

For the MIPS there are technically two types of delay slots.  One is
on the mips3 and earlier cpu's and it is respect to loads.

        load    addr, reg
        arbitray_insn           /* Load delay slot */

The rule on those cpu's is that the first instruction after a load
into a register cannot try to access the destination register of the
load, if it does it can get garbage.  This is case 1.

Case 2 is traditional RISC branch delay slots and is present on all
MIPS cpus.

/*1*/   {jal,bcond,b}   foo
/*2*/    arbitrary_insn
/*3*/   another_insn
 [ ... ]

/*4*/   yet_another_insn

The sequence of instructions executed will be [1, 2, 4] should the
branch be taken, else [1, 2, 3]

Ok, that was the second case, here comes where they fucked things up
massively on the MIPS.  Aparently they thought it was a "nice" idea to
hide the delay instruction mechanism of the cpu to the user by default
in most MIPS assemblers.  Therefore, by default when you feed
instructions to most MIPS assemblers the delay slots do not exist, the
assembler schedules the instructions and fills the delay slots for
you, so in this case you'd code as if it were a non-delay slotted

If you want to have the delay slots be visible and directly
controllable by you the coder, you need to specify the asm pseudo op:

        .set    noreorder
        [ ... ]
        .set    reorder

And further still, some assemblers have 'noreorder' set by default,
most do not.  You'll need to consult the docs for the assembler you
are using to see which is the case.

I was pretty ticked when I learned that MIPS assemblers move
instructions around on you behind your back, this is just simply

Yow! 11.26 MB/s remote host TCP bandwidth & ////
199 usec remote TCP latency over 100Mb/s   ////
ethernet.  Beat that!                     ////
-----------------------------------------////__________  o
David S. Miller, /_____________/ / // /_/ ><

<Prev in Thread] Current Thread [Next in Thread>