It's time for MIPS theology!
> Wrong :-) IDT offers a R3000 derived CPU plus the MIPS II extensions ...
Outside floating point, there's only a few differences from MIPS-1 to
o "Branch-likely" forms of branches, for more efficient loop closing.
o 'cache' operations - which could possibly be regarded as
o load-linked/store-conditional (MIPS'semaphore instructions).
LSI included these in their miniRISC, which they described as "32-bit
R4000" CPUs. LSI put them in in the belief they'd get better code
density, which you don't; branch-likely permits you to replace a nop
with a duplicated instruction, saving a clock but no space. Toshiba's
R3900 also picked up branch-likely, which is likely to become common
on future 32-bit MIPS CPUs.
I'd have said this makes miniRISC and R3900 about MIPS one-and-a-third.
No 32-bit CPU implements 'cache' or semaphores. IDT's 32-bit machines
are all MIPS-1.
> And I think the MIPS II extensions are interesting.
You're entitled to your opinion there... I though they were kind of
cute myself, particularly the semaphores.