The following simple calculation gives a picture of long memory
system latency impact...
Out of 100 single clock instruction executions:
97% Cache hit rate (to be considered rather good)
250ns Main memory latency (Rather usual).
100 / (97 + 3 * 33) = 0.51 = 51% efficiency = 67Mhz.
With 96% cache hit rate the result is 43.6%.
So my system is slow and i throw in a 200Mhz processor!
(same memory speed)
100 / (97 + 3 * 50) = 0.40 = 40% efficiency = 80Mhz. +13Mhz from 67!!
Vary the memory latency to experiment. Say you do some "magic" and make your
main memory return data in 100 ns, efficiency increases to 73.5%.
So for a couple of "design rules" :-)
o Don't go "off chip".
o If you have to go "off chip" be fast.
o Don't use "standard" buses to expand memory. (VME etc)
o If you have to use a bus, make sure it's a "low latency" bus.
o Each bus clock of latency added steal about 10% performance if
your bus clock is one third of the processor clock.
So if your L2 cache isn't considerable faster than your main memory
system it's a blody waste of time and money. However if we talk MP
systems things will be different.
Actually i have a 133MHz R4600 system without L2 cache and 16Mb DRAM
that compiles the entire OpenBSD faster than my ACER PICA R4400PC at
150Mhz with 512Kb L2 cache and 64Mb of DRAM.
There is more to performance than meets the eye.