> Hopefully this will be ready soon. For now my DECstation 5000/150 (R4000)
> does not boot with his 2.0.7 when compiled as R3000. It gets stuck in
> sys_cacheflush() somewhere. I mean that it does not boot to the same point
> where a R3000 DECstation would.
> I saw you rewrote most of that code, so that's what I am waiting for.
Yes, I rewrote this part of the code. It was simply nightmarish bad; I
implemented it in the very beginnings of Linux/MIPS where a version of
it-somehow-works-quality was sufficient but I really had to fix that. I
think I should explain it a bit.
In the old code sys_cacheflush(addr, size, flags) was both the syscall
cacheflush as well as the routine that was called from within the kernel.
The implementation did always flush the entire cache which is a
chainsaw massacre to the performance as it flushed the data cache about
90000 times and the I-cache about 25000 times when booting with a minimal
/etc/rc and no init. The implementation was also buggy as it flushed the
caches many times each times called.
In the new code sys_cacheflush() is only the syscall entry. sys_cacheflush()
verifies it's parameters for validity and calls cacheflush(). Note that
cacheflush() is not a function but a pointer to a function. Thus the
calling sequence from assembler is
and from C
Directly calls to sys_cacheflush() are no longer allows; instead call
cacheflush(). The prototype of cacheflush()
cacheflush(unsigned long addr, unsigned long size, unsigned int flags)
are similar to the old sys_cacheflush(). The flags parameter can be:
CF_DCACHE Flush the data cache
CF_ICACHE Flush the instruction cache
CF_BCACHE like (CF_DCACHE | CF_ICACHE)
CF_VIRTUAL Flush only virtual indexed caches like R4000 and better.
CF_PHYSICAL FLush only physical indexed caches like R2000, R3000, R6000.
The differenciation between virtual and physical cache improves
performance most for R3000 machines.
CF_ALL like (CF_VIRTUAL | CF_PHYSICAL).
More flags to come.
The actual cacheflush implementation is CPU model dependand as On MIPS the
special situation that several different implementations of CPU caches
exist. The CPU type dependand initialization in arch/mips/kernel/setup.c
and arch/mips/mips[1-4]/ take care of selection of the right routines.