From: Systemkennung Linux <firstname.lastname@example.org>
Date: Tue, 16 Jul 1996 04:24:02 +0200 (MET DST)
Yes, you're completly right. My plan was to put all the code dealing with
exception handling from head.S into mips[1-4]/. The parts of machine and
prozessor specific initialization that are in head.S should be rewritten
to C for maintainability and go into <arch/mips/<machine>/setup.c and
arch/mips/kernel/setup.c. What will finally be left in head.S is more or
less nothing but initializing a few CPU register.
This is not the way to do it. My current tree (which I hope to merge
with Ralf some time soon, there are over 2 megs of diffs between my
tree and his, 90% of it is not SGI specific) will eventually allow one
kernel to work on any MIPS out there, regardless of processor type
endianness etc. Added to this list my tree also:
1) Supports multiple TLB pids at once, Ralf flushed the entire TLB
every context switch, this was gross for performance.
2) Fine grained cache/tlb flushing on r4k. Again Ralf flushed the
entire thing all the time, again gross for performance.
3) Optimized memcpy/memset, basically I'm getting 8 times the
performance for pipe bandwidth than I did previously. csum and
csum_partial routines are being coded as I speak.
4) Not one #ifdef __RBLAH__ anywhere in the code.
5) One endian (little-endian) ext2 filesystems for both big and little
endian MIPS/Linux kernels. (code borrowed from Sparc port)
The shared library stuff is the easy part to do for you: nothing to do
because the minimal required support is already in the kernel and the
userland is completly o32 ABI/MIPS ISA I.
6) Support for n32 binaries is halfway complete.
7) %80 of all o32 IRIX binaries I have tested work with my IRIX
system call compatability code. This includes an IRIX dynamically
linked bash, all of my GNU cross development tools (I build kernels
on my INDY using IRIX binaries of the GNU utilities under
MIPS/Linux) and half of the lmbench suite.
8) Lots of stability work.
David S. Miller