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Re: Cascade interrupt

Subject: Re: Cascade interrupt
From: Systemkennung Linux <>
Date: Wed, 22 May 1996 00:31:15 +0200 (MET DST)
In-reply-to: <> from "Warner Losh" at May 21, 96 04:14:43 pm

> : PS: Rule of thumb for MIPS programmers:  If it doesn't work blame the
> :     caches ;-)
> Wonder if that is my floppy drive problem as well :-) :-) :-)
> Warner
> P.S.  I have my ISA (well EISA) buss mapped in to an address range,
> but the TLB entry says that it is non-cachable.  Would that still
> cause problems?  Or is that data that is passed back a DMA thing and I
> need to be careful about my caches...

The (E)ISA bus should be mapped uncachable; but as you say the floppy
data is DMA thing.  You need to enshure that you write all data to be
written on the floppy back into the RAM.  For reading flush the RAM address
range to be read from the cache then read the data.  It is important that
you don't access the address range to be read from the floppy during the
read or your cache might then once again contain old data.

For the chipset controlled second level caches you don't need to care
about flushing; the chipset should guarante consistence between l2 cache
and RAM.


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