> Small update about the RM200 stuff: the box reaches 133.12 BogoMIPS.
> Seems IDT worked on the branch taken penatly for v2.0 of the R4600.
Like the original R3000 (but not the R4000 and R4400) the R4600 has a
5-stage pipeline, and always executes the instruction which follows
any taken branch (the "branch delay slot"). So long as the branch
delay slot instruction does useful work (and it usually can on the
R4x00) there's no branch penalty for any R4600 CPU.
The R4600 was a complete redesign of the R4000-without-secondary-cache
made faster by:
o Changing the 8-stage R4000/4400 pipeline back to 5 stages;
o Bigger, cleverer (2x16Kbytes, 2-way set associative) caches;
o On a data cache miss the R4600 restarts as soon as it gets the data
it wants; the R4000/4400 waits for the whole line.
It really did work.
"Version 2.0" which Ralf referred to might be the R4700, an updated
pin-compatible design. But I think the only tweaks in the R4700 are
to the floating point unit. The real speed-up comes with the R5000,
which all reports indicate is pretty neat.
> So far this is the highes scoring MIPS box that I've tested myself
There's an interesting point. Potential MIPS users often ask us what
indication we can give them of performance for MIPS vs other
architectures. Does anyone out there on planet Linux have some
big-program "benchmarks" which give any leads to MIPS vs x86