Difference between revisions of "YAMON"
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[http://www.mips.com/content/Products/SoftwareTools/content_html/yamon YAMON]. (You need a ''free'' registration to download a documentation and sourcecode) | [http://www.mips.com/content/Products/SoftwareTools/content_html/yamon YAMON]. (You need a ''free'' registration to download a documentation and sourcecode) | ||
| + | |||
| + | An example of '''YAMON''' boot log on a MIPS Malta Board with a 24Kc core: | ||
| + | |||
| + | |||
| + | YAMON ROM Monitor, Revision 02.06. | ||
| + | Copyright (c) 1999-2004 MIPS Technologies, Inc. - All Rights Reserved. | ||
| + | |||
| + | For a list of available commands, type 'help'. | ||
| + | |||
| + | Compilation time = Mar 23 2004 16:50:44 | ||
| + | Board type/revision = 0x02 (Malta) / 0x00 | ||
| + | Core board type/revision = 0x07 (CoreFPGA-2) / 0x00 | ||
| + | System controller/revision = MIPS SOC-it 101 OCP / 1.3 SDR-FW-1:1 | ||
| + | FPGA revision = 0x0001 | ||
| + | MAC address = 00.d0.a0.00.04.2b | ||
| + | Board S/N = 0000000819 | ||
| + | PCI bus frequency = 33.33 MHz | ||
| + | Processor Company ID/options = 0x01 (MIPS Technologies, Inc.) / 0x00 | ||
| + | Processor ID/revision = 0x93 (MIPS 24Kc) / 0x60 | ||
| + | Endianness = Little | ||
| + | CPU/Bus frequency = 25 MHz / 25 MHz | ||
| + | Flash memory size = 4 MByte | ||
| + | SDRAM size = 64 MByte | ||
| + | First free SDRAM address = 0x800b3860 | ||
| + | |||
| + | '''Example of environment variables in YAMON | ||
| + | ''' | ||
| + | YAMON> set | ||
| + | |||
| + | baseboardserial (RO) 0000000819 | ||
| + | bootfile (R/W) | ||
| + | bootprot (R/W) tftp | ||
| + | bootserport (R/W) tty0 | ||
| + | bootserver (R/W) 0.0.0.0 | ||
| + | cpuconfig (R/W) | ||
| + | ethaddr (RO) 00.d0.a0.00.04.2b | ||
| + | fpu (R/W) | ||
| + | gateway (R/W) 0.0.0.0 | ||
| + | ipaddr (R/W) 10.0.0.100 | ||
| + | memsize (RO) 0x04000000 | ||
| + | modetty0 (R/W) 38400,n,8,1,hw | ||
| + | modetty1 (R/W) 38400,n,8,1,hw | ||
| + | prompt (R/W) YAMON | ||
| + | start (R/W) | ||
| + | startdelay (R/W) | ||
| + | subnetmask (R/W) 255.255.255.0 | ||
| + | yamonrev (RO) 02.06 | ||
| + | |||
| + | An '''srec''' kernel image can be loaded in YAMON as follows: | ||
| + | |||
| + | load tftfp://<tftp server name>/<srec file in /tftpboot> | ||
| + | |||
| + | for example, if I have a vmlinux.srec in /tftpboot on 10.0.0.139, then: | ||
| + | |||
| + | load tftp://10.0.0.139/vmlinux.srec | ||
Revision as of 18:58, 22 November 2004
YAMONâ„¢ is the ROM monitor used on MIPS Technologies' development boards.
YAMON. (You need a free registration to download a documentation and sourcecode)
An example of YAMON boot log on a MIPS Malta Board with a 24Kc core:
YAMON ROM Monitor, Revision 02.06.
Copyright (c) 1999-2004 MIPS Technologies, Inc. - All Rights Reserved.
For a list of available commands, type 'help'.
Compilation time = Mar 23 2004 16:50:44 Board type/revision = 0x02 (Malta) / 0x00 Core board type/revision = 0x07 (CoreFPGA-2) / 0x00 System controller/revision = MIPS SOC-it 101 OCP / 1.3 SDR-FW-1:1 FPGA revision = 0x0001 MAC address = 00.d0.a0.00.04.2b Board S/N = 0000000819 PCI bus frequency = 33.33 MHz Processor Company ID/options = 0x01 (MIPS Technologies, Inc.) / 0x00 Processor ID/revision = 0x93 (MIPS 24Kc) / 0x60 Endianness = Little CPU/Bus frequency = 25 MHz / 25 MHz Flash memory size = 4 MByte SDRAM size = 64 MByte First free SDRAM address = 0x800b3860
Example of environment variables in YAMON YAMON> set
baseboardserial (RO) 0000000819 bootfile (R/W) bootprot (R/W) tftp bootserport (R/W) tty0 bootserver (R/W) 0.0.0.0 cpuconfig (R/W) ethaddr (RO) 00.d0.a0.00.04.2b fpu (R/W) gateway (R/W) 0.0.0.0 ipaddr (R/W) 10.0.0.100 memsize (RO) 0x04000000 modetty0 (R/W) 38400,n,8,1,hw modetty1 (R/W) 38400,n,8,1,hw prompt (R/W) YAMON start (R/W) startdelay (R/W) subnetmask (R/W) 255.255.255.0 yamonrev (RO) 02.06
An srec kernel image can be loaded in YAMON as follows:
load tftfp://<tftp server name>/<srec file in /tftpboot>
for example, if I have a vmlinux.srec in /tftpboot on 10.0.0.139, then:
load tftp://10.0.0.139/vmlinux.srec