Difference between revisions of "XIO"

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XIO is a high-speed communications channel, used for most newer SGI systems ([[IP27]], [[IP30]], [[IP35]] - note the [[IP32|O2]] is NOT a XIO system). It's typically used in a switched star topology, the switch being called [[XBow]].
 
XIO is a high-speed communications channel, used for most newer SGI systems ([[IP27]], [[IP30]], [[IP35]] - note the [[IP32|O2]] is NOT a XIO system). It's typically used in a switched star topology, the switch being called [[XBow]].
  
XIO devices are called [[widget|widgets]]].
+
XIO devices are called [[widget|widgets]].
  
 
== Physical layer ==
 
== Physical layer ==

Revision as of 08:19, 5 November 2004

What is XIO?

XIO is a high-speed communications channel, used for most newer SGI systems (IP27, IP30, IP35 - note the O2 is NOT a XIO system). It's typically used in a switched star topology, the switch being called XBow.

XIO devices are called widgets.

Physical layer

XIO is usually used on a single-ended, source-synchronous physical layer (STL levels - SGI Transistor Logic). It's either an 8- or 16-bit channel, running at 400 MHz (using the dreaded compression connectors). There is also a version, called Crosstown, that uses normal cabling and differential PECL transmission.

Link layer

XIO contains a link-layer protocol (LLP) shared with CrayLink. Transfer is organized into micropackets. These contain a total of 128 bits of data and 32 bits of control. The control information encapsulates an 8 bit sideband (used by higher layers for framing), sequence numbers (for go-back-n link-layer retransmissions) and check bits (CRC-16).

The link layer is able to run both on 8- and 16-bit links, and if a upper half of a 16-bit link is non-functional, it will automatically revert to using the 8 lower bits.

Transactions

XIO supports basic read/write memory transactions. IRQs are sent through XIO by instructing a device to write a defined value to some register in another XIO widget. This write actually triggers the IRQ handling process in the interrupt controller. For instance, the HEART chip has such register at 0x80 in XIO widget space.

XIO addresses differ from physical processor addresses. They are two-part (widget-offset) and each XIO device is free to implement the translation from its unified memory space to the XIO address. BRIDGE and HEART are examples of two different approaches.

Device identification

There is no distinction between memory and configuration space in XIO. Instead, each XIO device has a predefined header that consists of a widget ID and several configuration registers.