TLB - Revision history

Ralf at 15:26, 26 September 2012

2012-09-26T15:26:51Z

Ralf: Make "page size" a link.

2006-08-29T13:55:21Z

Make "page size" a link.

McNeight: /* External Links */ revise link to wikipedia

2006-01-29T07:12:47Z

‎External Links: revise link to wikipedia

Ralf at 20:49, 4 May 2005

2005-05-04T20:49:05Z

Ralf: Make cache reference a wiki link

2004-11-08T13:38:11Z

Make cache reference a wiki link

Ralf: Fix some of the worst mistakes of the R6000 TLB description.

2004-11-07T18:40:31Z

Fix some of the worst mistakes of the R6000 TLB description.

Ralf at 14:26, 7 November 2004

2004-11-07T14:26:26Z

New page

== General ==
TLB is the abreviation for ''Translation Lookaside Buffer''. It's what MIPS calls the hardware unit which caches a few page table entries for translation of virtual to physical addresses. Over the years four major types of TLBs have been designed for MIPS processors.

== R2000-style TLB ==
This TLB always consists of 64 TLB entries. Each TLB entry maps a single page. The first 8 TLB entries are weired, that is they won't automatically be replaced by a ''tlbwr'' instruction. Each TLB entry only maps a single single page and the page size is 4kB. The TLB flushing is optimized by a 6-bit tag called ''PID''. TLB manipulation is done through 4 special instructions, ''tlbp'', ''tlbr'', ''tlbwi'', ''tlbwr''.

== R6000-style TLB ==
The [[R6000]] TLB is extremly unusual in that it in stores it's TLB entries in the last few lines of the second level cache. While this may seem totally [http://en.wikipedia.org/wiki/Braindead_%281992_movie%29 braindead] at first it doesn't actually harm because regular loads and stores are interleaved with TLB activity in the second level cache. Unlike other MIPS TLB designs on the R6000 MMU entries are manipulated though the cache instruction while the CPU is in a special mode that enables it to manipulate those cachelines that store the TLB entries. This part of the cache is also called ''TLB Slice''. Only the R6000 and it's slightly improved variant R6000A are using this kind of TLB organization.

== R4000-style TLB ==
This TLB has been implemented with a varying number of entries ranging from 32 to 64; 48 is probably the most common value. Each TLB entry can have a separate page size. Typically the page size ranges from 4kB to 16MB, in * 4 steps. A few CPUs supprt 64MB or even 256MB page size. On the low end a few TLBs also support 1kB pages. Each TLB entry maps an adjacent pair of pages. As the result the virtual address of a TLB entry needs to be aligned to twice the page size. This is an unusual restriction and may create slight problems in operating systems that were written in unawareness of this. The weird register permits changing the number of weird entries. Again TLB flushing is optimized by an 8-bit tag. Unlike on the R2000-style TLB it's called ''ASID'' however. Just like on the R2000 TLB manipulation is done through 4 special instructions, ''tlbp'', ''tlbr'', ''tlbwi'', ''tlbwr''.

== R8000-style TLB ==
The [[R8000]] being one of the oddball processors of the MIPS family of course had to have it's own TLB architecture also. TLB is organized as 3-way set associative. Each set contains 128 entries each mapping a single page. The page size can be set separately for ''kernel mode'' and ''user mode'' on the R8000 that is all pages in a particular mode will share the page size. Page sizes offered are 4kB, 8kB, 16kB, 64kB, 1MB, 4MB and 16MB. This means the R8000 TLB architecture is the only to offer 8kB. It's also the only which doesn't offer 256kB page size though it offers larger page sizes. The R8000 is the only MIPS CPU which uses this style of TLB. Similar to the [[R4000]] TLB manipulation is performed through 3 special instructions, ''tlbp'', ''tlbw'', ''tlbr''. That is there is no ''tlbwr'' instruction and the ''tlbwi'' instruction being the only TLB write instruction is named ''tlbw''.

== External Links ==
* http://en.wikipedia.org/wiki/TLB Wikipedia TLB article

@@ Line 16: / Line 16: @@
 == Linux support ==
 Linux supports R2000 and R4000-style TLBs which are used by the ''huge'' majority of all the systems that can possibly run Linux.  At the moment Linux only suports TLBs that support 4kB page size; there are plans to optionally increase the page size to 16kB or 64kB.  Alternate MMU organizations such at [[Block Address Translation]] registers are not supported.
 == External Links ==
 * [[wikipedia:Translation Lookaside Buffer|Wikipedia TLB article]]

@@ Line 9: / Line 9: @@
 == R4000-style TLB ==
-This TLB has been implemented with a varying number of entries ranging from 32 to 64; 48 is probably the most common value.  Each TLB entry can have a separate page size.  Typically the page size ranges from 4kB to 16MB, in *&nbsp;4 steps.  A few CPUs support 64MB or even 256MB page size.  On the low end a few TLBs also support 1kB pages.  Each TLB entry maps an adjacent pair of pages.  As the result the virtual address of a TLB entry needs to be aligned to twice the page size.  This is an unusual restriction and may create slight problems in operating systems that were written in unawareness of this.  The wired register permits changing the number of wired entries.  Again TLB flushing is optimized by an 8-bit tag.  Unlike on the R2000-style TLB it's called ''ASID'' however. Just like on the R2000 TLB manipulation is done through 4 special instructions, ''tlbp'', ''tlbr'', ''tlbwi'', ''tlbwr''.
+This TLB has been implemented with a varying number of entries ranging from 32 to 64; 48 is probably the most common value.  Each TLB entry can have a separate [[page size]].  Typically the page size ranges from 4kB to 16MB, in *&nbsp;4 steps.  A few CPUs support 64MB or even 256MB page size.  On the low end a few TLBs also support 1kB pages.  Each TLB entry maps an adjacent pair of pages.  As the result the virtual address of a TLB entry needs to be aligned to twice the page size.  This is an unusual restriction and may create slight problems in operating systems that were written in unawareness of this.  The wired register permits changing the number of wired entries.  Again TLB flushing is optimized by an 8-bit tag.  Unlike on the R2000-style TLB it's called ''ASID'' however. Just like on the R2000 TLB manipulation is done through 4 special instructions, ''tlbp'', ''tlbr'', ''tlbwi'', ''tlbwr''.
 == R8000-style TLB ==

← Older revision		Revision as of 07:12, 29 January 2006
Line 18:		Line 18:

	== External Links ==		== External Links ==
−	* ~~http~~:~~//en.wikipedia.org/wiki/TLB~~ Wikipedia TLB article	+	* [[wikipedia:Translation Lookaside Buffer\|Wikipedia TLB article]]

@@ Line 6: / Line 6: @@
 == R6000-style TLB ==
-The [[R6000]] TLB is extremly unusual in that it in stores it's TLB entries in the last few lines of it's large, external cache.  While this may seem totally [http://en.wikipedia.org/wiki/Braindead_%281992_movie%29 braindead] at first it doesn't actually harm because regular loads and stores are interleaved with TLB activity.  Unlike other MIPS TLB designs on the R6000 MMU entries are manipulated though the cache instruction while the CPU is in a special mode that enables it to manipulate those cachelines that store the TLB entries.  The part of the TLB that resides inside the CPU itself is called ''TLB Slice''.  Due to the close relation of cache and TLB the cache organization also enters the picture; it's physically indexed and virtually tagged. Only the R6000 and it's slightly improved variant R6000A are using this kind of TLB organization.
+The [[R6000]] TLB is extremly unusual in that it in stores it's TLB entries in the last few lines of it's large, external cache.  While this may seem totally [http://en.wikipedia.org/wiki/Braindead_%281992_movie%29 braindead] at first it doesn't actually harm because regular loads and stores are interleaved with TLB activity.  Unlike other MIPS TLB designs on the R6000 MMU entries are manipulated though the cache instruction while the CPU is in a special mode that enables it to manipulate those cachelines that store the TLB entries.  The part of the TLB that resides inside the CPU itself is called ''TLB Slice''.  Due to the close relation of [[Caches|cache]] and TLB the cache organization also enters the picture; it's physically indexed and virtually tagged. Only the R6000 and it's slightly improved variant R6000A are using this kind of TLB organization.
 == R4000-style TLB ==

@@ Line 13: / Line 13: @@
 == R8000-style TLB ==
 The [[R8000]] being one of the oddball processors of the MIPS family of course had to have it's own TLB architecture also.  TLB is organized as 3-way set associative.  Each set contains 128 entries each mapping a single page.  The page size can be set separately for ''kernel mode'' and ''user mode'' on the R8000 that is all pages in a particular mode will share the page size.  Page sizes offered are 4kB, 8kB, 16kB, 64kB, 1MB, 4MB and 16MB.  This means the R8000 TLB architecture is the only to offer 8kB.  It's also the only which doesn't offer 256kB page size though it offers larger page sizes.  The R8000 is the only MIPS CPU which uses this style of TLB.  Similar to the [[R4000]] TLB manipulation is performed through 3 special instructions, ''tlbp'', ''tlbw'', ''tlbr''.  That is there is no ''tlbwr'' instruction and the ''tlbwi'' instruction being the only TLB write instruction is named ''tlbw''.
 == External Links ==
 * http://en.wikipedia.org/wiki/TLB Wikipedia TLB article

@@ Line 3: / Line 3: @@
 == R2000-style TLB ==
-This TLB always consists of 64 TLB entries.  Each TLB entry maps a single page.  The first 8 TLB entries are weired, that is they won't automatically be replaced by a ''tlbwr'' instruction.  Each TLB entry only maps a single single page and the page size is 4kB.  The TLB flushing is optimized by a 6-bit tag called ''PID''.  TLB manipulation is done through 4 special instructions, ''tlbp'', ''tlbr'', ''tlbwi'', ''tlbwr''.
+This TLB always consists of 64 TLB entries.  Each TLB entry maps a single page.  The first 8 TLB entries are wired, that is they won't automatically be replaced by a ''tlbwr'' instruction.  Each TLB entry only maps a single single page and the page size is 4kB.  The TLB flushing is optimized by a 6-bit tag called ''PID''.  TLB manipulation is done through 4 special instructions, ''tlbp'', ''tlbr'', ''tlbwi'', ''tlbwr''.
 == R6000-style TLB ==
-The [[R6000]] TLB is extremly unusual in that it in stores it's TLB entries in the last few lines of the second level cache.  While this may seem totally [http://en.wikipedia.org/wiki/Braindead_%281992_movie%29 braindead] at first it doesn't actually harm because regular loads and stores are interleaved with TLB activity in the second level cache.  Unlike other MIPS TLB designs on the R6000 MMU entries are manipulated though the cache instruction while the CPU is in a special mode that enables it to manipulate those cachelines that store the TLB entries.  This part of the cache is also called ''TLB Slice''.  Only the R6000 and it's slightly improved variant R6000A are using this kind of TLB organization.
+The [[R6000]] TLB is extremly unusual in that it in stores it's TLB entries in the last few lines of it's large, external cache.  While this may seem totally [http://en.wikipedia.org/wiki/Braindead_%281992_movie%29 braindead] at first it doesn't actually harm because regular loads and stores are interleaved with TLB activity.  Unlike other MIPS TLB designs on the R6000 MMU entries are manipulated though the cache instruction while the CPU is in a special mode that enables it to manipulate those cachelines that store the TLB entries.  The part of the TLB that resides inside the CPU itself is called ''TLB Slice''.  Due to the close relation of cache and TLB the cache organization also enters the picture; it's physically indexed and virtually tagged. Only the R6000 and it's slightly improved variant R6000A are using this kind of TLB organization.
 == R4000-style TLB ==
-This TLB has been implemented with a varying number of entries ranging from 32 to 64; 48 is probably the most common value.  Each TLB entry can have a separate page size.  Typically the page size ranges from 4kB to 16MB, in *&nbsp;4 steps.  A few CPUs supprt 64MB or even 256MB page size.  On the low end a few TLBs also support 1kB pages.  Each TLB entry maps an adjacent pair of pages.  As the result the virtual address of a TLB entry needs to be aligned to twice the page size.  This is an unusual restriction and may create slight problems in operating systems that were written in unawareness of this.  The weird register permits changing the number of weird entries.  Again TLB flushing is optimized by an 8-bit tag.  Unlike on the R2000-style TLB it's called ''ASID'' however. Just like on the R2000 TLB manipulation is done through 4 special instructions, ''tlbp'', ''tlbr'', ''tlbwi'', ''tlbwr''.
+This TLB has been implemented with a varying number of entries ranging from 32 to 64; 48 is probably the most common value.  Each TLB entry can have a separate page size.  Typically the page size ranges from 4kB to 16MB, in *&nbsp;4 steps.  A few CPUs support 64MB or even 256MB page size.  On the low end a few TLBs also support 1kB pages.  Each TLB entry maps an adjacent pair of pages.  As the result the virtual address of a TLB entry needs to be aligned to twice the page size.  This is an unusual restriction and may create slight problems in operating systems that were written in unawareness of this.  The wired register permits changing the number of wired entries.  Again TLB flushing is optimized by an 8-bit tag.  Unlike on the R2000-style TLB it's called ''ASID'' however. Just like on the R2000 TLB manipulation is done through 4 special instructions, ''tlbp'', ''tlbr'', ''tlbwi'', ''tlbwr''.
 == R8000-style TLB ==