SB1

From LinuxMIPS
Revision as of 07:40, 16 May 2005 by Ralf (Talk | contribs)

Jump to: navigation, search

General

The SB1 (SiByte-1) core is a highperformance implementation of the MIPS64 architecture. It features 32kB instruction cache, 32kB data cache, 2 integer pipelines, 2 load/store pipelines and 2 fp pipelines. An SB1 core can issue upto 4 instructions per cycle.

Applications

The SB1 core is being used in Broadcom's BCM1250 system on a chip. The BCM1125 is similar but only contains a single SB1 core. The BCM1450 core contain four SB1 cores making it the highest performance SOC using the SB1 core.