SB1 - Revision history

ThS at 19:19, 31 October 2006

2006-10-31T19:19:26Z

Alec v: Broadcom's public web

2005-06-15T11:23:21Z

Broadcom's public web

Ralf at 07:40, 16 May 2005

2005-05-16T07:40:43Z

Ralf: /* General */

2005-04-27T20:30:53Z

‎General

Alec v: BCM1250

2004-12-02T07:50:30Z

BCM1250

Ralf at 00:26, 5 November 2004

2004-11-05T00:26:02Z

New page

== General ==
The '''SB1''' core is a highperformance implementation of the [[MIPS64]] architecture. It features 32kB instruction cache, 32kB data cache, 2 integer pipelines, 2 load/store pipelines and 2 fp pipelines. An SB1 core can issue upto 4 instructions per second.

== Applications ==
The SB1 core is beig used in Broadcom's [[BCM1250]] system on a chip. The [[BCM1250|BCM1125]] is similar but only contains a single SB1 core. The [[BCM1250|BCM1450]] core contain four SB1 cores making it the highest performance SOC using the SB1 core.

@@ Line 3: / Line 3: @@
 == Applications ==
-The SB1 core is being used in Broadcom's [[BCM1250]] system on a chip.  The [[BCM1250|BCM1125]] is similar but only contains a single SB1 core.  The [[BCM1250|BCM1450]] core contain four SB1 cores making it the highest performance SOC using the SB1 core.
+The SB1 core is being used in Broadcom's [[BCM1250]] system on a chip.  The [[BCM1250|BCM1125]] is similar but only contains a single SB1 core.  The [[BCM1250|BCM1480]] core contain four slightly updated SB1A cores making it the highest performance SOC using the SB1 core family.
 == External links ==
 * [http://sibyte.broadcom.com/public/index.html Broadcom's SiByte public web site]

← Older revision		Revision as of 11:23, 15 June 2005
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	== Applications ==		== Applications ==
	The SB1 core is being used in Broadcom's [[BCM1250]] system on a chip. The [[BCM1250\|BCM1125]] is similar but only contains a single SB1 core. The [[BCM1250\|BCM1450]] core contain four SB1 cores making it the highest performance SOC using the SB1 core.		The SB1 core is being used in Broadcom's [[BCM1250]] system on a chip. The [[BCM1250\|BCM1125]] is similar but only contains a single SB1 core. The [[BCM1250\|BCM1450]] core contain four SB1 cores making it the highest performance SOC using the SB1 core.
		+
		+	== External links ==
		+
		+	* [http://sibyte.broadcom.com/public/index.html Broadcom's SiByte public web site]

@@ Line 3: / Line 3: @@
 == Applications ==
-The SB1 core is beig used in Broadcom's BCM1250 system on a chip.  The BCM1125 is similar but only contains a single SB1 core.  The BCM1450 core contain four SB1 cores making it the highest performance SOC using the SB1 core.
+The SB1 core is being used in Broadcom's [[BCM1250]] system on a chip.  The [[BCM1250|BCM1125]] is similar but only contains a single SB1 core.  The [[BCM1250|BCM1450]] core contain four SB1 cores making it the highest performance SOC using the SB1 core.
-−
-== BCM1250 ==
-−
-BCM1250 is a chip that integrates ''two'' 64-bit MIPS CPU cores, each scalable to 600 MHz - 1 GHz, a large cache memory, and integrated I/O. The BCM1250 includes an on-chip 512K L2 Cache and a DDR memory controller that supports up to 2 GB of memory. Overall, the processor can support up to 50 Gbps of peak memory bandwidth. Integrated I/O includes three 10/100/1000 Ethernet MACs configurable to two 16-bit or three 8-bit FIFO interfaces, a 32-bit 33/66 MHz PCI bridge, support for HyperTransport, a high-speed I/O bus for chip-to-chip interconnect, two serial interfaces, a generic bus for direct connection to boot flash, PCMCIA support and on-chip debug features. An evaluation board platform, called the [[Swarm|BCM91250A]], uses of all the interfaces on the BCM1250, and can be used with any ATX 2.0 compliant case and power supply. Off-the-shelf peripherals including PCI graphics adapters, USB keyboards and mice, and ATA hard disks can be added. The board supports VxWorks 5.4, Linux 2.4 running in 32-bit mode with SMP support, and NetBSD 1.5 running in 32-bit mode.

@@ Line 1: / Line 1: @@
 == General ==
-The '''SB1''' (SiByte-1) core is a highperformance implementation of the [[MIPS64]] architecture.  It features 32kB instruction cache, 32kB data cache, 2 integer pipelines, 2 load/store pipelines and 2 fp pipelines.  An SB1 core can issue upto 4 instructions per second.
+The '''SB1''' (SiByte-1) core is a highperformance implementation of the [[MIPS64]] architecture.  It features 32kB instruction cache, 32kB data cache, 2 integer pipelines, 2 load/store pipelines and 2 fp pipelines.  An SB1 core can issue upto 4 instructions per cycle.
 == Applications ==