Difference between revisions of "SB1"

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== Applications ==
 
== Applications ==
The SB1 core is being used in Broadcom's [[BCM1250]] system on a chip.  The [[BCM1250|BCM1125]] is similar but only contains a single SB1 core.  The [[BCM1250|BCM1450]] core contain four SB1 cores making it the highest performance SOC using the SB1 core.
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The SB1 core is being used in Broadcom's [[BCM1250]] system on a chip.  The [[BCM1250|BCM1125]] is similar but only contains a single SB1 core.  The [[BCM1250|BCM1480]] core contain four slightly updated SB1A cores making it the highest performance SOC using the SB1 core family.
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== External links ==
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* [http://sibyte.broadcom.com/public/index.html Broadcom's SiByte public web site]

Latest revision as of 19:19, 31 October 2006

General

The SB1 (SiByte-1) core is a highperformance implementation of the MIPS64 architecture. It features 32kB instruction cache, 32kB data cache, 2 integer pipelines, 2 load/store pipelines and 2 fp pipelines. An SB1 core can issue upto 4 instructions per cycle.

Applications

The SB1 core is being used in Broadcom's BCM1250 system on a chip. The BCM1125 is similar but only contains a single SB1 core. The BCM1480 core contain four slightly updated SB1A cores making it the highest performance SOC using the SB1 core family.

External links