Difference between revisions of "SB1"
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== General == | == General == | ||
| − | The '''SB1''' (SiByte-1) core is a highperformance implementation of the [[MIPS64]] architecture. It features 32kB instruction cache, 32kB data cache, 2 integer pipelines, 2 load/store pipelines and 2 fp pipelines. An SB1 core can issue upto 4 instructions per | + | The '''SB1''' (SiByte-1) core is a highperformance implementation of the [[MIPS64]] architecture. It features 32kB instruction cache, 32kB data cache, 2 integer pipelines, 2 load/store pipelines and 2 fp pipelines. An SB1 core can issue upto 4 instructions per cycle. |
== Applications == | == Applications == | ||
| − | The SB1 core is | + | The SB1 core is being used in Broadcom's [[BCM1250]] system on a chip. The [[BCM1250|BCM1125]] is similar but only contains a single SB1 core. The [[BCM1250|BCM1480]] core contain four slightly updated SB1A cores making it the highest performance SOC using the SB1 core family. |
| − | == | + | == External links == |
| − | + | * [http://sibyte.broadcom.com/public/index.html Broadcom's SiByte public web site] | |
Latest revision as of 19:19, 31 October 2006
[edit] General
The SB1 (SiByte-1) core is a highperformance implementation of the MIPS64 architecture. It features 32kB instruction cache, 32kB data cache, 2 integer pipelines, 2 load/store pipelines and 2 fp pipelines. An SB1 core can issue upto 4 instructions per cycle.
[edit] Applications
The SB1 core is being used in Broadcom's BCM1250 system on a chip. The BCM1125 is similar but only contains a single SB1 core. The BCM1480 core contain four slightly updated SB1A cores making it the highest performance SOC using the SB1 core family.
